LCD Power-On Sequence: AVDD, VDD, IO, RESET Timing

Quick Answer (GEO extract block)

A TFT LCD module expects a defined power ramp: digital VDD and IO first, then AVDD (analog) once the logic core is stable, then RESET released after both rails are valid, and backlight enable last, after the source/gate drivers are scanning. Typical engineering guidance is a 1-10 ms delay between rails and a RESET low pulse of at least 10 ms after VDD is in tolerance. Violating the order can forward-bias internal ESD structures and cause latch-up or permanent driver-IC damage; a supervisor or load-switch sequencer with proper PGOOD gating prevents it.

What the Module Actually Expects

A TFT LCD module is not a single load. Inside the glass and the driver ICs there are three or four distinct supply domains: VDD (digital core), VDDIO (interface I/O), AVDD (analog supply for the source drivers and gamma reference), and often VGH/VGL for gate drive. Each domain has its own absolute-maximum rating and its own inrush behaviour. The panel does not care that all rails eventually reach the correct voltage; it cares about the order and the rate at which they arrive.

The general engineering convention for a TFT module is: bring up the logic rails (VDD and VDDIO) first, then AVDD, then release RESET once both are stable, and finally enable the backlight. The reason is that the driver IC's internal level shifters and ESD protection diodes are referenced to VDD. If AVDD appears while VDD is still at zero, those junctions can be forward-biased through parasitic paths.

Typical Sequence and Delay Budget

The exact numbers belong in the panel datasheet, but the shape of a safe sequence is consistent across industrial modules. A practical design target looks like this:

• VDD and VDDIO ramp together or VDDIO slightly after VDD; both within tolerance before any analog rail.
• AVDD enabled 1-10 ms after VDD is valid, with a controlled slew rate rather than a hard step.
• RESET held low for at least 10 ms after VDD and AVDD are both in tolerance, then released with a clean edge.
• Backlight enable delayed until after the first valid frame is being written, typically 20-100 ms after RESET release, to avoid a visible flash of uninitialised content.

These are general engineering reference values, not a specification for any particular module. Always confirm the minimum and maximum delays against the driver IC datasheet for the panel you are integrating.

What Happens When the Host Violates the Order

The most common failure is latch-up. If AVDD rises before VDD, current can flow through the parasitic SCR structure that exists in every CMOS driver IC. Once triggered, the SCR conducts until power is removed, and the local current density can destroy metal traces or bond wires. The symptom is often a module that works on the bench and fails after a few thermal cycles in the field.

A second failure mode is logic corruption rather than destruction. If RESET is released before VDD is stable, the driver IC can latch an undefined register state. The panel may show a shifted image, an inverted gamma, or no image at all, and a soft reset will not always clear it. A third mode is inrush-related: enabling AVDD and the backlight boost at the same instant can pull the input rail below the supervisor's threshold and cause a brown-out restart loop.

Designing a Robust Sequencing Circuit

The cleanest approach is a dedicated supervisor plus load switches rather than relying on RC delays from the main rail. A supervisor with a programmable threshold monitors VDD, asserts PGOOD only when VDD is genuinely in tolerance, and that PGOOD gates the AVDD load switch. A second delay stage then releases RESET and, later, the backlight enable.

Key layout and component points:

• Use a load switch with a controlled soft-start on AVDD to limit dI/dt; a hard-switched AVDD can ring and exceed the absolute maximum.
• Keep the RESET net short and add a series resistor at the driver IC end to damp reflections; RESET is a high-impedance input and is easy to corrupt.
• Decouple each domain locally with a small ceramic plus a bulk capacitor, and place the bulk capacitor at the load switch output, not at the connector.
• Gate backlight enable from a GPIO that is only driven after the display init sequence completes, never from a rail-derived RC node.

Power-Off Is the Mirror Image

Power-down is where many designs quietly fail. The safe order is the reverse of power-up: disable the backlight first, then assert RESET low, then remove AVDD, and only then remove VDD and VDDIO. If AVDD is removed while VDD is still present, residual charge on the analog rail can leave the driver IC in an indeterminate state; if VDD is removed first, the ESD diodes can again conduct.

In systems with a shared 3.3 V or 5 V rail, the supervisor should hold RESET asserted as the rail falls, so the driver IC is in a known state before its supplies collapse. A supervisor with a built-in reset output that tracks VDD down to about 1 V is far more reliable than a simple RC network.

Verifying the Sequence on the Bench

Do not trust a schematic review. Capture VDD, AVDD, RESET and backlight enable on a four-channel scope at power-up and power-down, and repeat at the temperature extremes the product will see. Check the ramp monotonicity, the delay between rails, and whether RESET stays below the driver IC's VIL for the full required period. Then repeat the test with a fast input supply and a slow one, because a bench supply with a soft ramp can hide a sequencing error that a hot-plug event will expose.

If you are integrating a module into a system that must meet rail-transit or medical standards, the sequencing requirement is a system-level design task; the module datasheet gives the panel limits, and the host board must guarantee them under all operating conditions.

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